A New Platform for Functional Representation, Synthesis, and Verification

Improvements in the structure of a circuit at the logic level can offer significant benefits, but the consequences on the final design parameters are often difficult to predict. The algorithms and tools necessary to more fully evaluate potential optimizations and to iterate between logic synthesis and other components of the design flow are often prohibitively costly, time consuming, and difficult to acquire and integrate, especially for academic researchers. The OpenAccess database provides an industrystandard data model, and the OpenAccess Gear library a set of pre-written tools and algorithms, and the combination of the two offers researchers an attractive platform for the fast development of more complete design flows to incorporate into and further their research. We introduce an extension of this platform into the functional domain. A straightforward but flexible functional representation is defined, a set of tools for logic synthesis, verification, and technology mapping are provided, and an example design flow from RTL Verilog to a structural netlist is outlined.